IEEE

Pioneering 8-bit Comparator Architecture with Independent (INDEP) Gate Control

Abstract: This paper presents a novel 8-bit comparator architecture designed using the Independent Gate Control (INDEP) technique to enhance speed and energy efficiency. The proposed design integrates ...
IEEE

A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator

Abstract: This paper presents a 1-GS/s 7-bit 3-then-1 bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). To strike a good balance among the noise performance, power ...