Electronic Design

Low-Voltage 4:1 Analog Multiplexer Does One Thing—and Does It Very Well

The continuing need for basic analog-function components. The characteristics of a tiny 4:1 multiplexer/1:4 demultiplexer for analog signals. How an evaluation board simplifies checkout of this analog ...
IEEE

FPGA Design and Implementation of BCH Encoders and Decoders Using Pipelined Architecture for High Throughput Applications

This paper presents the design and FPGA implementation of a high-throughput BCH (n,k) encoder and decoder using a fully pipelined architecture. Unlike conventional designs based on finite state ...
IEEE

40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

Abstract: This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used ...
GitHub

mdp4_lcdc_encoder.c

mdp4_write(mdp4_kms, REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(0), MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(0x08) | MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(0x05) | MDP4_LCDC_LVDS_MUX ...
GitHub

SB_TX_PACKET_ENCODER_WRAPPER.sv

UCIe PHY layer RTL. Contribute to phyliphyli/GP_UCIe development by creating an account on GitHub.