IEEE

FPGA Design and Implementation of BCH Encoders and Decoders Using Pipelined Architecture for High Throughput Applications

This paper presents the design and FPGA implementation of a high-throughput BCH (n,k) encoder and decoder using a fully pipelined architecture. Unlike conventional designs based on finite state ...
IEEE

Exploring the Power of Vision Transformer (ViT) and MLP-Mixer in Image Classification: A Comparative Study and Prospects for ViT-Mixer Architecture

Abstract: For image classification tasks, the convolutional neural network (CNN) has so far been the automatic choice. However, the revolutionary triumph of the Transformer architecture in NLP ...