IEEE

FPGA Design and Implementation of BCH Encoders and Decoders Using Pipelined Architecture for High Throughput Applications

This paper presents the design and FPGA implementation of a high-throughput BCH (n,k) encoder and decoder using a fully pipelined architecture. Unlike conventional designs based on finite state ...
GitHub

Brain-to-Text '25: Neural Speech Decoding

Deep learning models for decoding intracortical neural activity during attempted speech into text. This repository contains our team's implementation for the COMP 433 Fall 2025 course project, ...
IEEE

Temporal Convolutional and Fusional Transformer Model With Bi-LSTM Encoder-Decoder for Multi-Time-Window Remaining Useful Life Prediction

Abstract: Health prediction is crucial for ensuring reliability, minimizing downtime, and optimizing maintenance in industrial systems. Remaining Useful Life (RUL) prediction is a key component of ...