IEEE

A 16×16 High-Utilization Systolic Array Hardware Accelerator for Long-Sequence Flash-Attention Computation in Transformer

Abstract: This paper presents a Flash-Attention accelerator design methodology based on a 16×16 high-utilization systolic array architecture for long-sequence Transformer applications. By ...
IEEE

Scalable Low-latency Systolic Arrays using Toroidal and Bi-Directional Dataflows

Abstract: Systolic arrays (SAs) for matrix multiplication are commonly used in machine learning (ML), wireless communication, and signal processing. Inherently offering high throughput with good data ...
GitHub

Neural Network Accelerator — Systolic Array in Verilog

Neural Network Accelerator — Systolic Array in Verilog A custom neural network accelerator built from scratch in Verilog, featuring a weight-stationary systolic array that performs matrix ...
GitHub

Systolic-Processor-Architecture /DPU_array_matrix_multiplication_3

DPU0: DPU_matrix_multiplication port map(A0,B0,CLK,clear,S03,S01,O0); DPU1: DPU_matrix_multiplication port map(A1,S01,CLK,clear,S14,S12,O1); DPU2: DPU_matrix ...