IEEE

FPGA Design and Implementation of BCH Encoders and Decoders Using Pipelined Architecture for High Throughput Applications

This paper presents the design and FPGA implementation of a high-throughput BCH (n,k) encoder and decoder using a fully pipelined architecture. Unlike conventional designs based on finite state ...
IEEE

GURNet: A Gated U-Shaped Encoder-Decoder Predictor for Reversible Data Hiding

Abstract: The existing deep learning based reversible data hiding (RDH) predictors typically adopt standard convolutions for extracting features, which inherently fails to capture contextual ...