GitHub

A simple signed booth multiplier that produces accurate results for signed multiplications

I have designed a 4-bit signed Booth multiplier in Verilog. The design supports signed multiplication using Booth's algorithm, efficiently handling positive and negative operands. The repository ...
IEEE

Improved Modular Multiplication Algorithms Using Solely IEEE 754 Binary Floating-Point Operations

Abstract: In this paper, we propose three modular multiplication algorithms that use only the IEEE 754 binary floating-point operations. Several previous studies have used floating-point operations to ...
IEEE

Fama : An FPGA-Oriented Multi-Scalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design

Abstract: Multi-scalar multiplication (MSM) is the primary computational bottleneck in zero-knowledge proof protocols. To address this, we introduce FAMA, an FPGA-oriented MSM accelerator developed ...
GitHub

sh1-sh2-cpu-core-architecture.md

This document may, wholly or partially, be subject to change without notice. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the ...