San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

Since DAC 2005, there has been extensive discussion about using Statistical Static Timing Analysis (SSTA) to verify current and future generations of designs manufactured at 90 nm or below. Given the ...

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...

In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot ...