EDN

Phase-Locked Loop Applications

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...
Electronic Design

Integrated Phase Lock Loop Replaces Crystal Oscillators

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 1)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
EDN

Good behavioral model simulation: key to predicting first-order PLL synthesizer performance (Part 1 of 2)

In this article, the phase noise of a closed-loop, phase-locked loop (PLL) synthesizer is simulated using Agilent RF Design Environment (RFDE) and Advanced Design System (ADS) tools. The critical ...
EurekAlert!

Figure 2. Die micrograph of the proposed digital phase locked loop (PLL) (IMAGE)

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...